Characterization of CMOS Defects using Transient Signal Analysis

We present the results of hardware experiments designed to determine the relative contribution of CMOS coupling mechanisms to off-path signal variations caused by common types of defects. The transient signals measured in defect-free test structures coupled to defective test structures through internodal coupling capacitors, the power supply, the well and substrate are analyzed in the time and frequency domain to determine the characteristics of the signal variations produced by seven types of CMOS defects. The results of these experiments are used in the development of a failure analysis technique based on the analysis of transient signals. Transient Signal Analysis (TSA) [1] is a defect detection technique for digital CMOS devices that is based on the analysis of transient signal behavior. The method analyzes the voltage transient waveforms measured simultaneously at multiple test points while a logic signal transition is applied to the primary inputs. These transient waveforms characterize the physical components of the coupling network in a digital device. Variations in the transient signals across different devices are a direct consequence of changes in the resistive, inductive and capacitive components of the coupling network, as well as in the gain and threshold voltage characteristics of the transistors. Variations in the values of these circuit parameters may result from process tolerance effects, or they may result from defects. In previous work, we demonstrated that it is possible to detect defects by analyzing the small signal variations at test points that are not on logic signal propagation paths from the defect site [2][3]. We indicated that this is possible because of the coupling mechanisms that exist in CMOS devices, namely the resistive and capacitive coupling through the power supply and the wells, as well as the parasitic capacitive and inductive coupling between conductors. These mechanisms couple the large signal variations of faults at defective nodes to adjacent conductors where they can be measured as small signal variations at test point nodes. We also demonstrated that by cross-correlating the signals measured simultaneously at different topological locations on the device, it is possible to distinguish between signal variations caused by process tolerance effects and those caused by defects [4]. This is true because process tolerance effects tend to be global, causing signal changes on all test points of the device. In contrast , signal variations caused by a defect tend to be regional and more pronounced on test points closest to the defect site. …